The present invention relates to low defect silicon carbide wafers and their use as precursors for semiconductor purposes, and to seeded sublimation growth of large, high-quality silicon carbide single crystals.
The invention is also related to the following copending and commonly assigned U.S. applications Ser. No. 10/628,189 filed Jul. 28, 2003 for Growth of Ultra-High Purity Silicon Carbide Crystals in an Ambient Containing Hydrogen; Ser. No. 10/628,188 filed Jul. 28, 2003 for Reducing Nitrogen Content in Silicon Carbide Crystals by Sublimation Growth in a Hydrogen-Containing Ambient; Ser. No. 10/707,898 filed Jan. 22, 2004 for Silicon Carbide on Diamond Substrates and Related Devices and Methods; Ser. No. 60/522,326 filed Sep. 15, 2004 for Seed Preparation for the Growth of High Quality Large Size Silicon Carbide Crystals; Ser. No. 10/915,095 filed Aug. 10, 2004 for Seed and Seedholder Combinations for High Quality Growth of Large Silicon Carbide Single Crystals; and Ser. No. 10/876,963 filed Jun. 25, 2004 for One Hundred Millimeter High Purity Semi-Insulating Single Crystal Silicon Carbide Wafer. The contents of these applications are likewise incorporated entirely herein by reference.
Silicon carbide has found use as semiconductor material for various electronic devices and purposes in recent years. Silicon carbide is especially useful due to its physical strength and high resistance to chemical attack. Silicon carbide also has excellent electronic properties, including radiation hardness, high breakdown field, a relatively wide band gap, high saturated electron drift velocity, high-temperature operation, and absorption and emission of high-energy photons in the blue, violet, and ultraviolet regions of the spectrum.
Single crystal silicon carbide is often produced by a seeded sublimation growth process. In a typical silicon carbide growth technique, the seed crystal and a source powder are both placed in a reaction crucible which is heated to the sublimation temperature of the source and in a manner that produces a thermal gradient between the source and the marginally cooler seed crystal. The thermal gradient encourages vapor phase movement of the materials from the source to the seed followed by condensation upon the seed and the resulting bulk crystal growth. The method is also referred to as physical vapor transport (PVT).
In a typical silicon carbide growth technique, the crucible is made of graphite and is heated by induction or resistance, with the relevant coils and insulation being placed to establish and control the desired thermal gradient. The source powder is silicon carbide, as is the seed. The crucible is oriented vertically, with the source powder in the lower portions and the seed positioned at the top, typically on the seed holder; see U.S. Pat. No. 4,866,005 (reissued as No. Re34,861) the contents of which are incorporated entirely herein by reference. These sources are exemplary, rather than limiting, descriptions of modern seeded sublimation growth techniques.
Although the density of structural defects in silicon carbide bulk crystals has been continually reduced in recent years, relatively high defect concentrations still appear and have been found to be difficult to eliminate, e.g. Nakamura et al., “Ultrahigh quality silicon carbide single crystals,” Nature, Vol. 430, Aug. 26, 2004, page 1009. When dislocations lying in the basal plane (c-plane) of the crystal exists on the surface of the seed crystal substrate, these dislocations may persist in the subsequent growth of the crystal. These defects can cause significant problems in limiting the performance characteristics of devices made on the substrates, or in some cases can preclude useful devices altogether.
Current seeded sublimation techniques for the production of large bulk single crystals of silicon carbide typically result in a higher than desired concentration of defects on the basal plane growing surface of the silicon carbide crystal. Higher concentrations of defects can cause significant problems in limiting the performance characteristics of devices made on the crystals, or substrates resulting from the crystals. For example, a typical micropipe defect density in the basal plane of some commercially available silicon carbide wafers can be on the order of 100 per square centimeter (cm−2). A megawatt device formed in silicon carbide, however, requires a defect free area on the order of 0.4 cm−2. Thus, obtaining large single crystals that can be used to fabricate large surface area devices for high-voltage, high current applications remain a worthwhile goal.
Although small samples of low-defect silicon carbide have been available, a broader commercial use of silicon carbide requires larger samples, and in particular, larger wafers. By way of comparison, 100 mm (4″) silicon wafers have been commercially available since 1975 and 150 mm (6″) silicon wafers became available in 1981. Gallium arsenide (GaAs) is also commercially available in both 4″ (100 mm) and 6″ (150 mm) wafers. Thus, the commercial availability of 50 mm (2″) and 75 mm (3″) SiC wafers lags behind these other materials and to some extent limits the adoption and use of SiC in a wider range of devices and applications.
The nature and description of specific defects is generally well understood in the crystal growth art. Micropipes are common defects that can be found in SiC and can develop or propagate during the seeded sublimation production of SiC crystals. Other defects that may be present in SiC crystals include threading, edge, and screwdislocations, along with hexagonal voids, stacking faults and basal plane dislocations. If these defects remain in the SiC crystal, then resulting devices grown on the crystal may incorporate these defects.
A micropipe is a hollow core super-screw dislocation with its Burgers vector typically lying along the c-axis. A number of causes have been proposed or identified for the generation of micropipes. These include excess materials such as silicon or carbon inclusions, extrinsic impurities such as metal deposits, boundary defects, and the movement or slippage of partial dislocations. See e.g. Powell et al., Growth of Low Micropipe Density SiC Wafers, Materials Science Forum, Vols. 338-340, pp 437-440 (2000).
Hexagonal voids are flat, hexagonal platelet-shaped cavities in the crystal that often have hollow tubes trailing beneath them. Some evidence shows that micropipes are associated with hexagonal voids. A relatively recent discussion of such defects (exemplary and not limiting) is set forth in Kuhr et al., Hexagonal Voids And The Formation Of Micropipes During SiC Sublimation Growth, Journal of Applied Physics, Volume 89, No. 8, page 4625 (April 2001).
Recent research indicates that problems in the bulk crystals produced in a seeded sublimation technique can originate with the seed itself and the manner in which it is physically handled; e.g., Sanchez et al Formation Of Thermal Decomposition Cavities In Physical Vapor Transport Of Silicon Carbide, Journal of Electronic Materials, Volume 29, No. 3, page 347 (2000). Sanchez uses the term “micropipe” to describe, “approximately cylindrical voids with diameters in the range of 0.1 μm to 5 μm that form at the core of superscrew dislocations aligned parallel or nearly parallel to the [0001] axis” Id. at 347. Sanchez refers to larger voids (“diameters from 5 μm to 100 μm”) as, “thermal decomposition cavities,” and opines that micropipes and thermal decomposition cavities arise from different causes. Id.
Accordingly, producing larger high quality bulk single crystals of silicon carbide with low basal plane defect levels in crystals formed in the seeded sublimation system remains a constant technical commercial goal.
Basal plane dislocations are typically positioned within a (0001) plane either intersecting a surface or creating a closed loop. For most applications the primary concern is the number of basal plane dislocations that will intersect the wafer surface and hence propagate into the subsequently deposited epitaxial layer. When the SiC wafer is to be used as a substrate for epitaxial growth, it is critical to consider the number of dislocations that intersect the wafer surface. This number is measured by conducting a defect etch of the wafer that will reveal pits at the dislocation locations. For this measurement the number of dislocations intersecting the surface will increase as the offcut (“off-axis”) angle from the <0001> direction is increased. Most commercial SiC wafers are presently produced with an offcut angle of 4 degrees, however any other angle can be used from zero to 90 degrees. Counting the number of dislocations (observable as straight or curved lines) in a given representative area gives a representative basal plane defect density.
In the case where the substrate is used as an active device layer, the density of defects in the bulk material is also of concern and the most appropriate measurement is the total line length of basal plane dislocations in a given volume of material. This is measured by considering a small volume of material (such as that contained in a sample for X-ray topography) and measuring the total length of dislocations observed. This length is then divided by the volume of the sample to provide the total line length of basal plane dislocation per cm3.